On Wed, Aug 24, 2016 at 01:19:50PM +0200, Christophe Leroy wrote: > No I can't see any special reason for this. But I can confirm that without > the two additional clock cycles with CS\ high, the commands are not taken > into account. Right, I just looked at the datasheet and it says in the serial control interface section that it needs a three clock cycle idle state. Clearly the designers weren't having a very good day when they did the digital here but based on that you probably only need to send an extra byte with chip select deasserted at the end of the transfer to satisfy it rather than padding at both start and end. Like I say it'll need a new core feature though.
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