Some components requires some clock cycles with chipselect off before
or/and after the data transfer done with CS on.
Typically IDT801034 QUAD PCM CODEC datasheet states "Note *: CCLK should
have one cycle before CS goes low, and two cycles after CS goes high".
The only way I see to achieve that is to transfer a 4 bits word with CS
off before and after the data.
I've not found any way to do so in the current SPI subsystem
implementation, is there any ?
If not, what would be the best approach to implement that ?
Cheers,
Christophe
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