Le 24/08/2016 à 13:12, Mark Brown a écrit :
On Wed, Aug 24, 2016 at 01:03:57PM +0200, Christophe Leroy wrote:
CS is asserted inconditionnaly at begining of the function, regardless of
its previous status.
Then for all transfers but the last, when cs_change is set CS is deasserted
for 10us then re-asserted.
If cs_change is set for the last tranfer, the function leaves CS asserted.
So I don't see how I can transfer some data with CS de-asserted.
Oh, yes we reset at the start of the function. You'd need to change the
core to support this, and even then your compatibility with controllers
is going to be very limited.
What is this device, is there some reason for this?
No I can't see any special reason for this. But I can confirm that
without the two additional clock cycles with CS\ high, the commands are
not taken into account.
This device (IDT 821034) is a quad PCM codec for audio that I want to
implement within ALSA.
Christophe
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