Re: How to handle SPI components requiring heading/leading clock cycles with CS off

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Le 24/08/2016 à 12:56, Mark Brown a écrit :
On Wed, Aug 24, 2016 at 12:49:55PM +0200, Christophe Leroy wrote:
Le 24/08/2016 à 11:44, Mark Brown a écrit :

If you leave the device with cs_change set so the chip select is low it
should do the right thing after the first message, though obviously you
won't be able to share the chip select then.

What is needed is to get some SPI clock cycles with CS off i.e. CS high.
With cs_change, CS will remain low i.e. CS active

No, it'll change chip select so if it's already set it'll deassert and
if you leave it deasserted at the end of a transaction it should leave
it deasserted.


In function  spi_transfer_one_message(), my understanding is that:

CS is asserted inconditionnaly at begining of the function, regardless of its previous status. Then for all transfers but the last, when cs_change is set CS is deasserted for 10us then re-asserted.
If cs_change is set for the last tranfer, the function leaves CS asserted.

So I don't see how I can transfer some data with CS de-asserted.

Christophe
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