Re: How to handle SPI components requiring heading/leading clock cycles with CS off

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On Wed, Aug 24, 2016 at 01:03:57PM +0200, Christophe Leroy wrote:

> CS is asserted inconditionnaly at begining of the function, regardless of
> its previous status.
> Then for all transfers but the last, when cs_change is set CS is deasserted
> for 10us then re-asserted.
> If cs_change is set for the last tranfer, the function leaves CS asserted.

> So I don't see how I can transfer some data with CS de-asserted.

Oh, yes we reset at the start of the function.  You'd need to change the
core to support this, and even then your compatibility with controllers
is going to be very limited.

What is this device, is there some reason for this?

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