Re: How to handle SPI components requiring heading/leading clock cycles with CS off

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Le 24/08/2016 à 11:44, Mark Brown a écrit :
On Tue, Aug 23, 2016 at 06:10:48PM +0200, Christophe Leroy wrote:

The only way I see to achieve that is to transfer a 4 bits word with CS off
before and after the data.
I've not found any way to do so in the current SPI subsystem implementation,
is there any ?
If not, what would be the best approach to implement that ?

If you leave the device with cs_change set so the chip select is low it
should do the right thing after the first message, though obviously you
won't be able to share the chip select then.



What is needed is to get some SPI clock cycles with CS off i.e. CS high.
With cs_change, CS will remain low i.e. CS active
     _   _   _   _   _   _   _   _   _   _   _   _   _   _   _   _
CLK   |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_|
__   ___                                 ___________
CS      |_______________________________|           |_______________

This means we need to transmit some data with CS high, otherwise the SPI chip doesn't deliver clock.


Christophe
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