> > > > >
> > > > > It's still selecting from multiple PLLs.
> > > > >
> > > > > > I don't know whether "divider" module exists or not. If it
> > > > > > exists, it should be part of PLL or between PLL and MUX.
> > > > > > wherever it was, the
> > > > > device tree binding is appropriate.
> > > > >
> > > > > The device tree binding is unnecessarily complicated.
> > > > >
> > > > > > The P3041RM shows exactly each PLL has 2 outputs which
> > > > > > definitely have
> > > > > no "divider" at all.
> > > > >
> > > > > That diagram is a bit weird -- one of the outputs is used as is,
> > > > > and the other is split into 1/2 and 1/4. It doesn't really
> > > > > matter though; the end result is the same. We're describing the
> > > > > programming interface, not artwork choices in the manual.
> > > > >
> > > > > -Scott
> > > > >
> > > > If the device tree needs to be modified, could you give me your
> > > suggestions?
> > >
> > > My suggestion is to have only one output per PLL node. The MUX node
> > > would have one input per PLL. Dividers would be handled internally
> > > to the MUX driver.
> > >
> > > -Scott
> > >
> > I don't think your suggestion is constructive.
>
> Hmm?
>
> > Your suggestion is on the premise of that the "divider" is part of
> > MUX, And I think it should be part of PLL.
> > MUX can't CREATE clock which PLL can. So my thought is more reasonable.
> > If the device tree documents like what you said, it would have few help
> for driver.
> > The reason is obvious that the driver is still going to deal with the
> "divider"
> > detail which varies from platform to platform.
> > I will document as it was unless you prove your suggestion.
>
> I can't follow this. My point is that my suggestion better matches the
> programming model, and is simpler.
>
> -Scott
>
I didn't see how your suggestion is a better matching.
OSC ----> PLL1 ----> mux ----> CPU
| |
|--> PLL2 --|
........
As your suggestion, the clock tree looks like the above.
In this case, the MUX driver will not know the divider
details(/2, /4, or /3).
I think the MUX should act like "switch" which choose one
of the input clock as a output clock. It should not CREATE
clock(like PLL1/2, PLL1/4).
The purpose of clock driver is to establish the clock tree.
The clock tree will not be established in your suggestion
because the divider is missing, we don't know where PLL/2 comes from.
If you really like your proposal, it should be changed to this:
OSC ------> PLL1 -----> PLL1 /1 ---------> MUX ------->CPU
| |___> PLL1 /2 _______|
| |
|____> PLL2 -----> PLL2 /2 -------|
|___> PLL2/ 4 _______|
(it is possible that PLLs have different divider).
Regards,
Yuantian
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