> > > > >
> > > > The device tree makes that quite clear.
> > >
> > > You chose to model it that way in the device tree; that doesn't make
> > > it clear that the hardware works that way or that it's a good way to
> > > model it.
> > >
> > > > Each PLL has several output which MUX node can take from.
> > >
> > > Point out where in the hardware documentation it says this. What I
> > > see is a PLL that has one output, and a MUX register that can choose
> > > from multiple PLL and divider options.
> > >
> > Take T4240 for example: see section 4.6.5.1 , (Page 141) in T4240RM Rev.
> D, 09/2012.
>
> That shows the dividers as being somewhere in between the PLL and the MUX.
> The MUX is where the divider is selected. There's nothing in the PLL's
> programming interface that relates to the dividers. As such it's simpler
> to model it as being part of the MUX.
>
> -Scott
>
I don't know whether it is simpler, but "modeling divider as being part of the MUX"
is your guess, right?
If the "divider" is included in MUX, the MUX would not be called "MUX".
I don't know whether "divider" module exists or not. If it exists, it should be part
of PLL or between PLL and MUX. wherever it was, the device tree binding is appropriate.
The P3041RM shows exactly each PLL has 2 outputs which definitely have no "divider" at all.
Regards,
Yuantian
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