> -----Original Message-----
> From: Wood Scott-B07421
> Sent: 2013年10月15日 星期二 6:13
> To: Tang Yuantian-B29983
> Cc: Wood Scott-B07421; Mark Rutland; devicetree@xxxxxxxxxxxxxxx;
> linuxppc-dev@xxxxxxxxxxxxxxxx; Li Yang-Leo-R58472
> Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in device
> tree
>
> On Fri, 2013-10-11 at 21:52 -0500, Tang Yuantian-B29983 wrote:
> > Thanks for your review.
> >
> > > -----Original Message-----
> > > From: Wood Scott-B07421
> > > Sent: 2013年10月12日 星期六 3:07
> > > To: Mark Rutland
> > > Cc: Tang Yuantian-B29983; devicetree@xxxxxxxxxxxxxxx; linuxppc-
> > > dev@xxxxxxxxxxxxxxxx; Li Yang-Leo-R58472
> > > Subject: Re: [PATCH v5] powerpc/mpc85xx: Update the clock nodes in
> > > device tree
> > >
> > > I'm not sure I understand the "_0"/"_1" part, though. Doesn't each
> > > PLL just have one output, which the consumer may choose to divide by
> > > 2 (or in some cases 4)? Why does that division need to be exposed
> > > in the device tree as separate connections to the parent clock?
> > >
> > The device tree makes that quite clear.
>
> You chose to model it that way in the device tree; that doesn't make it
> clear that the hardware works that way or that it's a good way to model
> it.
>
> > Each PLL has several output which MUX node can take from.
>
> Point out where in the hardware documentation it says this. What I see
> is a PLL that has one output, and a MUX register that can choose from
> multiple PLL and divider options.
>
Take T4240 for example: see section 4.6.5.1 , (Page 141) in T4240RM Rev. D, 09/2012.
> > It is not a runtime decision.
>
> Hmm? It's a register you write to.
>
I mean the number of PLL output or the division of PLL is not a runtime decision.
Which output of PLL the MUX can take is a runtime decision.
Regards,
Yuantian
> -Scott
>
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