On Sun, 2013-10-20 at 21:55 -0500, Tang Yuantian-B29983 wrote: > I didn't see how your suggestion is a better matching. > > OSC ----> PLL1 ----> mux ----> CPU > | | > |--> PLL2 --| > ........ > As your suggestion, the clock tree looks like the above. > In this case, the MUX driver will not know the divider > details(/2, /4, or /3). When is there ever a /3? > I think the MUX should act like "switch" which choose one > of the input clock as a output clock. It should not CREATE > clock(like PLL1/2, PLL1/4). > The purpose of clock driver is to establish the clock tree. > The clock tree will not be established in your suggestion > because the divider is missing, we don't know where PLL/2 comes from. > > If you really like your proposal, it should be changed to this: > > OSC ------> PLL1 -----> PLL1 /1 ---------> MUX ------->CPU > | |___> PLL1 /2 _______| > | | > |____> PLL2 -----> PLL2 /2 -------| > |___> PLL2/ 4 _______| > > (it is possible that PLLs have different divider). Do we actually have (or expect) a situation where the PLLs have different dividers, or even where the same bit setting in the MUX register means a different divider from one chip to another (within the same MUX compatible string)? If so, then I agree that we should go with your approach. The way Freescale documents things in chip manuals rather than in block manuals, with little bits of information different in each chip manual, makes it hard to figure out this sort of thing. From the examples I looked at, it seemed pretty consistent that the low 2 bits of CLKSEL in the MUX were the log2 of the divider. Are there any chips that don't adhere to this? -Scott -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
