Re: PATCH Prevent spi-dw write transaction split

[Trent Piepho <tpiepho@xxxxxxxxxx>]

On Mon, 2018-12-03 at 11:00 +0000, Gil Beniamini wrote:
> Hi Mark,
> 
> > The goal is just to connect a GPIO (and GPIO controlled by any GPIO
> > controller) to the chip select of the device and make sure that the
> > chip select output of the controller isn't routed anywhere where
> > it'll do any harm.
> 
> If you have an existing board where spi-dw native chip-select has
> been used instead of other independent gpios, than you can't use
> "gpio-cs" to re-own
> & control those chip-select, and has a potential tx-transaction-split 
> problem that must be solved via the attached software patch.

I'm not working on CycloneV right now, but this is contrary to what I
recall.

If you have used SPIM0 SS0 as your chip select, can you not change the
mux of that pin to GPIO60, if you use pin generalio12, or gpio66 if on
pin generalio27, or gpio57 if on mixed2io3?

See the sysmgr register generalio12, which allows one of the two
possible locations for spim0 ss0 to be muxed to a gpio.

https://www.intel.com/content/altera-www/global/en_us/index/documentati
on/sfo1410143707420.html#sfo1410067905435

Each of the HPS pins is controlled by one of these mux registers.  So
you can mux any of them to gpio.

It's also possible to mux any of them to loanio and control them from
the FPGA.  The SPI master control line signals can be routed to the
fpga too.  You can fixup the CS in fpga logic that way.