RE: PATCH Prevent spi-dw write transaction split

[Gil Beniamini <GilB@xxxxxxxxx>]

Hi Trent,
You Said:
> It's just a minor change in the device tree to switch to using GPIO based chip select.  There is no big re-write.
> Disabling interrupts is not very nice to all those users who do not need it.
> And if I understand correctly, after the fifo fills you still have the same problem that the master we de-assert chip select if the fifo then empties, which your patch doesn't address.
> What's more, IIRC, switching from write to read also causes a cs pulse on this controller in certain spi modes.
> So really your just mitigating one of many ways using the native cs on this controller can fail.  Use a gpio CS and solve all of them.
Using GPIO was the first solution we tried to implement, the problem was not defining "cs-gpios" in the device-tree,
but rather the CYCLONE5 (socfpga).
our FPGA expert tried to define the GPIOs using his DSP tools,
his conclusion was that in CYCLONE5 the DesignWare-SPI chip-select is hard-wired and can't be replaced by individual GPIO(s).
That left us with only option as the spi-dw software patch that I am pushing.
As for transfer(s) bigger than the TX-FIFO, the suggested "patch" can't address that issue, but I assume that for SPI device
which support large transfers can't be sensitive to byte-order and chip-select!

Gil Beniamini
Gilat Satellite Networks – R&D
gilb@xxxxxxxxx
Phone: (972)-3-9252427 Fax:(972)-3-9293240
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