Re: PATCH Prevent spi-dw write transaction split

[Trent Piepho <tpiepho@xxxxxxxxxx>]

On Sun, 2018-11-18 at 06:47 +0000, Gil Beniamini wrote:
> Hi Trent,
> You said:
> >  "Can you instead use gpio chip select?  This would prevent master
> > de- asserting it when the fifo empties.  You can probably pinmux
> > your chip to use the same pin as it uses now, but in gpio mode.
> > Or try to use DMA, which will be much more reliable."
> 
> My answer is that we are using SPI-DW driver AS-IS, disabling the
> auto ChipSelect by the driver and do it via GPIO ourselves, or doing
> DMA for small transactions (our spi defined in dtb as "enable-dma =
> <1>"),
> is a big rewrite, than the "ATOMIC" copy loop of few bytes to the tx-
> fifo.

It's just a minor change in the device tree to switch to using GPIO
based chip select.  There is no big re-write.

Disabling interrupts is not very nice to all those users who do not
need it.

And if I understand correctly, after the fifo fills you still have the
same problem that the master we de-assert chip select if the fifo then
empties, which your patch doesn't address.

What's more, IIRC, switching from write to read also causes a cs pulse
on this controller in certain spi modes.

So really your just mitigating one of many ways using the native cs on
this controller can fail.  Use a gpio CS and solve all of them.