On Tue, Nov 20, 2018 at 06:07:58PM +0000, Trent Piepho wrote: > On Tue, 2018-11-20 at 12:20 +0000, Gil Beniamini wrote: > > his conclusion was that in CYCLONE5 the DesignWare-SPI chip-select is > > hard-wired and can't be replaced by individual GPIO(s). > I have used Cyclone5 SPI with GPIO CS, so I am quite sure it can be > done. ... > The internal SPI controller signals routed to the FPGA only show up > with the native CS. Perhaps this is what your fpga designer is talking > about, and he simple tried to route them to a FPGA pin. The goal is just to connect a GPIO (and GPIO controlled by any GPIO controller) to the chip select of the device and make sure that the chip select output of the controller isn't routed anywhere where it'll do any harm. > I seem to recall that there was an additional internal SPI signal and > there was a way to add some logic in the FPGA to combine this with the > CS signals to stop CS de-assert in the middle. Ideally you could talk to Designware about how unhelpful their design is, I know some other users have tried and at least one ended up modifying their instance of the SPI IP to add the required feature - see the cs_override stuff in the driver in -next.
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