RE: PATCH Prevent spi-dw write transaction split

[Gil Beniamini <GilB@xxxxxxxxx>]

> I have used Cyclone5 SPI with GPIO CS, so I am quite sure it can be done.
> The pinmux of the (48?) HPS only pins is handled through device tree.
> If you are using some of those, then you just use the device tree to set them.
> To use FPGA pins, you can create an Altera GPIO device in your design, which Linux supports,
> to add more GPIOs on any FPGA pin you want.
> Just add the device "altr,pio-1.0" at the address you choose in in the memory region of the appropriate hsp2fpga bridge.
> Last CycV design I did had four blocks FPGA gpios.  It's also a really easy way to get a signal from Liunx userspace to the FPGA.  You probably already have some.
> The internal SPI controller signals routed to the FPGA only show up with the native CS.  Perhaps this is what your fpga designer is talking about, and he simple tried to route them to a FPGA pin.
> I seem to recall that there was an additional internal SPI signal and there was a way to add some logic in the FPGA to combine this with the CS signals to stop CS de-assert in the middle.
Hi Tend, We'll re-explore the GPIO as SPI CS, probably be next week.
Hopefully this time we'll be more successful. I'll update after we'll have the retry results.

Gil Beniamini
Gilat Satellite Networks – Defense R&D
gilb@xxxxxxxxx
Phone: (972)-3-9252427 Fax:(972)-3-9293240

-----Original Message-----
From: Trent Piepho [mailto:tpiepho@xxxxxxxxxx]
Sent: Tuesday, November 20, 2018 8:08 PM
To: broonie@xxxxxxxxxx; Gil Beniamini <GilB@xxxxxxxxx>
Cc: linux-spi@xxxxxxxxxxxxxxx; thor.thayer@xxxxxxxxxxxxxxx; Shay Dahan <ShayD@xxxxxxxxx>; Ronen Tamam <RonenT@xxxxxxxxx>
Subject: Re: PATCH Prevent spi-dw write transaction split

On Tue, 2018-11-20 at 12:20 +0000, Gil Beniamini wrote:
> his conclusion was that in CYCLONE5 the DesignWare-SPI chip-select is
> hard-wired and can't be replaced by individual GPIO(s).
> That left us with only option as the spi-dw software patch that I am
> pushing.
> As for transfer(s) bigger than the TX-FIFO, the suggested "patch"
> can't address that issue, but I assume that for SPI device which
> support large transfers can't be sensitive to byte-order and
> chip-select!

I have used Cyclone5 SPI with GPIO CS, so I am quite sure it can be done.

The pinmux of the (48?) HPS only pins is handled through device tree.
If you are using some of those, then you just use the device tree to set them.

To use FPGA pins, you can create an Altera GPIO device in your design, which Linux supports, to add more GPIOs on any FPGA pin you want.  Just add the device "altr,pio-1.0" at the address you choose in in the memory region of the appropriate hsp2fpga bridge.  Last CycV design I did had four blocks FPGA gpios.  It's also a really easy way to get a signal from Liunx userspace to the FPGA.  You probably already have some.

The internal SPI controller signals routed to the FPGA only show up with the native CS.  Perhaps this is what your fpga designer is talking about, and he simple tried to route them to a FPGA pin.

I seem to recall that there was an additional internal SPI signal and there was a way to add some logic in the FPGA to combine this with the CS signals to stop CS de-assert in the middle.
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