RE: PATCH Prevent spi-dw write transaction split

[Gil Beniamini <GilB@xxxxxxxxx>]

On 20Nov18 Trend said:
>> I have used Cyclone5 SPI with GPIO CS, so I am quite sure it can be done.
>> The pinmux of the (48?) HPS only pins is handled through device tree.
>> If you are using some of those, then you just use the device tree to set them.
>> To use FPGA pins, you can create an Altera GPIO device in your design,
>> which Linux supports, to add more GPIOs on any FPGA pin you want.
>> Just add the device "altr,pio-1.0" at the address you choose in in the memory region of the appropriate hsp2fpga bridge.
>> Last CycV design I did had four blocks FPGA gpios.  It's also a really easy way to get a signal from Liunx userspace to the FPGA.  You probably already have some.
>> The internal SPI controller signals routed to the FPGA only show up with the native CS.  Perhaps this is what your fpga designer is talking about, and he simple tried to route them to a FPGA pin.
>> I seem to recall that there was an additional internal SPI signal and there was a way to add some logic in the FPGA to combine this with the CS signals to stop CS de-assert in the middle.
On 21Nov18 I said:
> Hi Tend, We'll re-explore the GPIO as SPI CS, probably be next week.
> Hopefully this time we'll be more successful. I'll update after we'll have the retry results.
My update is:
I am told that we have already existing designs (in production and in the field),
where the GPIO which has been selected during the board design are those
that the CycloneV internal DesignWare (SPI) is using as it's Chip-Select.
So on these boards we face the Chip-Select drop issue upon FIFO underflow and
must have our suggested software patch.
While on some other designs where other general GPIOs has been selected,
cs-gpios can be defined in device-tree and there is no problem at all.
Bottom line: So for those "naïve" designs where the internal SPI dedicated gpio pins has
already  been selected as SPI chip-select, for bounded transfers (less than Tx FIFO size)
there is no other way than the suggested patch.

Gil Beniamini
Gilat Satellite Networks – Defense R&D
gilb@xxxxxxxxx
Phone: (972)-3-9252427 Fax:(972)-3-9293240

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