Hi Wolfram and Geert,
> Subject: Re: [PATCH] clk: renesas: r9a07g044: Fix 533MHz PLL2/3 clock
> multiplier and divider values
>
>
> > Perhaps the "if (freq > (ccccc))" check in
> > renesas_sdhi_clk_update() can be slightly relaxed, so it allows e.g. a
> > 0.1% (or 1/1024th?) higher clock rate than requested?
>
> Yes, we can do that.
freq = clk_round_rate(ref_clk, new_clock << i);
+ pr_err("%s## freq/new_clock=%llu/%llu",__func__,freq,(new_clock << i));
if (freq > (new_clock << i)) {
This is how it ended up in selecting 400MHz clk.
For (new_clock << i) = 533333332, clk_round_rate becomes 400MHz and it selected that clock.
[ 18.364948] renesas_sdhi_clk_update## freq/new_clock=533333333/4266666656
[ 18.364980] renesas_sdhi_clk_update## freq/new_clock=533333333/2133333328
[ 18.371871] renesas_sdhi_clk_update## freq/new_clock=533333333/1066666664
[ 18.381122] renesas_sdhi_clk_update## freq/new_clock=400000000/533333332
[ 18.388033] renesas_sdhi_clk_update## freq/new_clock=533333333/4266666656
[ 18.394936] renesas_sdhi_clk_update## freq/new_clock=533333333/2133333328
[ 18.401829] renesas_sdhi_clk_update## freq/new_clock=533333333/1066666664
[ 18.408760] renesas_sdhi_clk_update## freq/new_clock=400000000/533333332
Cheers,
Biju
