Hi Biju,
Thanks for your patch!
On Tue, Sep 13, 2022 at 9:44 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> As per the HW manual (Rev.1.10 Apr, 2022) clock rate for 533MHz PLL2 and
> PLL3 clocks should be 533 MHz, but with current multiplier and divider
> values this resulted to 533.333333 MHz.
>
> This patch updates the multiplier and divider values for 533 MHz PLL2 and
> PLL3 clocks so that we get the exact (533 MHz) values.
Does this matter? Is there anything that doesn't work (well) because
of this?
> Fixes: 373bd6f487562e ("clk: renesas: r9a07g044: Add SDHI clock and reset entries")
> Fixes: f294a0ea9d12a6 ("clk: renesas: r9a07g044: Add clock and reset entries for SPI Multi I/O Bus Controller")
> Fixes: 31d5ef2f565d23 ("clk: renesas: r9a07g044: Add M4 Clock support")
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> --- a/drivers/clk/renesas/r9a07g044-cpg.c
> +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> @@ -113,10 +113,10 @@ static const struct {
> DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
> DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
> DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
> - DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
> + DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 533, 1600),
I highly doubt the actual hardware is not using a by-3 divider....
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
