RE: [PATCH] clk: renesas: r9a07g044: Fix 533MHz PLL2/3 clock multiplier and divider values

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Hi Geert,

> Subject: Re: [PATCH] clk: renesas: r9a07g044: Fix 533MHz PLL2/3 clock
> multiplier and divider values
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, Sep 13, 2022 at 9:44 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> > As per the HW manual (Rev.1.10 Apr, 2022) clock rate for 533MHz PLL2
> > and
> > PLL3 clocks should be 533 MHz, but with current multiplier and divider
> > values this resulted to 533.333333 MHz.
> >
> > This patch updates the multiplier and divider values for 533 MHz PLL2
> > and
> > PLL3 clocks so that we get the exact (533 MHz) values.
> 
> Does this matter? Is there anything that doesn't work (well) because of
> this?

Yes, SDHI performance gone bad as it selects 533Mhz clock instead of 400Mhz.
Similar case for RZ/G2UL, which I am testing it now.

Previously:-
533333333->src clk0
400000000->src clk1
266666666->src clk2

Now:-
533000000->src clk0
400000000->src clk1
266500000->src clk2

If I am correct, with wrong values, it ended
up in 533333332(parent rate= 133333333 *4) and requested rate 533333333
and it selected best rate as 400000000. 
 
Cheers,
Biju

> 
> > Fixes: 373bd6f487562e ("clk: renesas: r9a07g044: Add SDHI clock and
> > reset entries")
> > Fixes: f294a0ea9d12a6 ("clk: renesas: r9a07g044: Add clock and reset
> > entries for SPI Multi I/O Bus Controller")
> > Fixes: 31d5ef2f565d23 ("clk: renesas: r9a07g044: Add M4 Clock
> > support")
> > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > @@ -113,10 +113,10 @@ static const struct {
> >                 DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL,
> 1, 1000),
> >                 DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL,
> PLL146_CONF(0)),
> >                 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
> > -               DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
> > +               DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 533,
> > + 1600),
> 
> I highly doubt the actual hardware is not using a by-3 divider....
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds




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