Re: [PATCH] clk: renesas: r9a07g044: Fix 533MHz PLL2/3 clock multiplier and divider values

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> Perhaps the "if (freq > (new_clock << i))" check in
> renesas_sdhi_clk_update() can be slightly relaxed, so it allows
> e.g. a 0.1% (or 1/1024th?) higher clock rate than requested?

Yes, we can do that.

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