> > > Perhaps the "if (freq > (ccccc))" check in > > > renesas_sdhi_clk_update() can be slightly relaxed, so it allows e.g. a > > > 0.1% (or 1/1024th?) higher clock rate than requested? > > > > Yes, we can do that. ... > This is how it ended up in selecting 400MHz clk. May I ask you to implement it? You have the HW to check which margin is actually needed.
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