Hi Fabio,
On 25/06/2021 02:20, Fabio Estevam wrote:
Hi Ian,
On Wed, Jun 9, 2021 at 2:28 PM Ian Arkver <ian.arkver.dev@xxxxxxxxx> wrote:
Page 55 of the ADV7280-M HW Ref Manual shows how the CLK and DATA lanes
can be (separately) forced into Ultra Low Power State. It mentions that
when exiting ULPS it transmits the ULPS exit sequence, though it doesn't
define what that sequence is. Perhaps this sequence includes
transitioning through LP-11 enough to keep the CSI-2 RX happy?
I measured the CLK and DATA lines and they are stuck at 0.
LP-11 means CLK and DATA at 1, right?
So this is what I tried as per your suggestion:
--- a/drivers/media/i2c/adv7180.c
+++ b/drivers/media/i2c/adv7180.c
@@ -505,6 +505,8 @@ static int adv7180_s_power(struct v4l2_subdev *sd, int on)
struct adv7180_state *state = to_state(sd);
int ret;
ret = mutex_lock_interruptible(&state->mutex);
if (ret)
return ret;
@@ -512,6 +514,20 @@ static int adv7180_s_power(struct v4l2_subdev *sd, int on)
ret = adv7180_set_power(state, on);
if (ret == 0)
state->powered = on;
+
+ if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
+ pr_err("**** Put MIPI CSI in LP-11\n");
+ adv7180_csi_write(state, 0x26, 0x00);
+ msleep(100);
+ adv7180_csi_write(state, 0x26, 0x80);
+ msleep(100);
+ adv7180_csi_write(state, 0x26, 0xc0);
+ msleep(100);
+ adv7180_csi_write(state, 0x26, 0xe0);
+ msleep(100);
+ adv7180_csi_write(state, 0x26, 0xf0);
+ msleep(100);
+ }
It looks like you're putting the clock and data into ULPS, but I don't
see you clearing that mode again. It's the transition *out* of ULPS that
I think would go through LP-11 and hopefully awaken the i.MX6 CSI.
However, I'm only guessing from the ref manual. Unfortunately I don't
have an ADV7280-M to try it with. I've only got the BT656 versions.
Good luck!
Ian
mutex_unlock(&state->mutex);
return ret;
but still see CLK and DATA at 0.
Any ideas?
Thanks,
Fabio Estevam
