Hi,
On 09/06/2021 08:20, Philipp Zabel wrote:
Hi Fabio,
On Tue, 2021-06-08 at 23:34 -0300, Fabio Estevam wrote:
Hi Philipp,
On Tue, Jun 8, 2021 at 4:09 AM Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> wrote:
The i.MX6 CSI-2 RX needs to see the LP-11 low power state on the lanes
during streamon (before it calls the ADV7280-M s_stream(1)). That's
where the LP-11 timeout error occurs.
According to the ADV7280(-M) datasheet, "after the ADV7280-M is
programmed, the clock lanes exit low power mode and remain in high speed
mode until the part is reset or powered down."
So it appears the ADV7280-M has to be freshly powered on in s_power(1)
Page 55 of the ADV7280-M HW Ref Manual shows how the CLK and DATA lanes
can be (separately) forced into Ultra Low Power State. It mentions that
when exiting ULPS it transmits the ULPS exit sequence, though it doesn't
define what that sequence is. Perhaps this sequence includes
transitioning through LP-11 enough to keep the CSI-2 RX happy?
Just a thought.
Regards,
Ian
What do you mean by freshly powered on?
That the ADV7280-M is in the state before "the clock lanes exit low
power mode" due to being "programmed". Basically I was hoping that after
the initial reset sequence, and after power on, before the CSI-2
registers are written, the clock lanes are in LP-11 state (and stay
there until then).
Unfortunately that doesn't appear to be the case below ...
for this to work. Is the ADV7280-M powerdown GPIO connected properly on
your board? Moving the CSI-2 configuration from s_power to s_stream was
exactly the right thing to do in my mind.
Just as a test, if you remove the CSI-2 register writes from either
s_power and s_stream from the adv7180 driver completely, do you still
run into the LP-11 timeout? If the CSI-2 TX never leaves the low power
state, I would expect seeing the clock lane timeout instead
If I do this test, the first time I run the pipeline I get LP-11, the
second time I get clock lane timeout.
... at least the first time.
So now I wonder what happens between the first and second time (in
s_stream? in s_power(0)?) that does put the lanes into LP-11 from
whatever state they were in before. When you get the clock lane timeout,
is phy_state = 0x610? Does it stay there when you repeat this again?
regards
Philipp
