Hi Philipp, On Tue, Jun 8, 2021 at 4:09 AM Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> wrote: > The i.MX6 CSI-2 RX needs to see the LP-11 low power state on the lanes > during streamon (before it calls the ADV7280-M s_stream(1)). That's > where the LP-11 timeout error occurs. > > According to the ADV7280(-M) datasheet, "after the ADV7280-M is > programmed, the clock lanes exit low power mode and remain in high speed > mode until the part is reset or powered down." > So it appears the ADV7280-M has to be freshly powered on in s_power(1) What do you mean by freshly powered on? > for this to work. Is the ADV7280-M powerdown GPIO connected properly on > your board? Moving the CSI-2 configuration from s_power to s_stream was > exactly the right thing to do in my mind. > > Just as a test, if you remove the CSI-2 register writes from either > s_power and s_stream from the adv7180 driver completely, do you still > run into the LP-11 timeout? If the CSI-2 TX never leaves the low power > state, I would expect seeing the clock lane timeout instead If I do this test, the first time I run the pipeline I get LP-11, the second time I get clock lane timeout. Thanks, Fabio Estevam
