On Mon, Jun 09, 2014 at 11:56:17AM -0700, Mathew Li wrote: > Hi Marc, Hi Mathew, > > I got few more questions. Let's say we are going to the guest, and > injecting an interrupt. Consider the following scenario: > > 1. So basically the HYP mode code is trying to writing 01 (interrupt > pending) to one of the list registers. this injects a *virtual* interrupt to the GIC. > 2. Guest resumes and immediately gets a virtual interrupt. yes, assuming that interrupts is enabled in the cpsr of the guest. > 3. Before the guest ACKs the interrupt, hardware interrupt arrives and > guest gets preempted but it had enough time to run few instructions. > 4. Guest exits and host sees the interrupt host now sees the *hardware* interrupt, this is completely unrelated to the fact that a *virtual* interrupt was generated on the list registers. > , serves it and we get back > to restoring the guest to continue running. Now at this point when HYP > mode code again restores 01 (interrupt pending) in the list register, > wouldn't the guest see another virtual interrupt as soon as it gets > resumed even through it has not ACK'd the last instance? It would see the exact same situation as it did before. If the guest executed a few instructions of its ISR when the hardware interrupt arrived and the hardware trapped to hyp mode, KVM will restore the CPU in the exact same state, which would be a few instructions into the ISR but prior to reading the acknowledge register, in your example. There is no concept of "another virtual interrupt", if there are one or more pending LRs on the VGIC, it will raise a virtual interrupt to the guest CPU and the guest CPU will only know details of such an interrupt when it actually acks that interrupt. > > Another question is, in HYP mode code, does it matter if we restore > HCR register 1st or the list registers 1st? > I don't believe it does for GICv2, for GICv3 there was some dependency with HCR.VI and HCR.VF. -Christoffer > > On Wed, Jun 4, 2014 at 7:44 AM, Christoffer Dall > <christoffer.dall@xxxxxxxxxx> wrote: > > On Wed, Jun 04, 2014 at 02:12:57PM +0100, Marc Zyngier wrote: > >> On 04/06/14 13:58, Christoffer Dall wrote: > >> > On Tue, Jun 03, 2014 at 05:39:16PM +0100, Marc Zyngier wrote: > >> >> On Tue, Jun 03 2014 at 5:24:01 pm BST, Mathew Li <mathew.li100@xxxxxxxxx> wrote: > >> >>> Thanks for all the answers Marc. I had one more question: > >> >>> > >> >>> Theoretically, can a pcpu running in kernel mode (i.e. non-HYP mode) > >> >>> write to the list register in vcpu control interface of another pcpu > >> >>> (i.e. different from the writing pcpu)? > >> >> > >> >> There are two things here: > >> >> - Not sure if you could write to the GICH range from EL1. I don't see > >> >> anything in the spec that forbids it, but that clearly contrary to the > >> >> spirit of the architecture. > >> > > >> > FWIW, this actually works just fine on a TC2. > >> > >> Yeah, I don't think the source EL is being carried out on the bus, only > >> the S/NS bit. But that's not very nice, and definitely impossible with > >> GICv3 and system registers. > >> > > Yup, the v7 KVM code did look nice that way though and made for some > > relatively easy optimizations, but I couldn't measure any noticable > > effect from those on TC2 so I abanded that code completely. > > > > -Christoffer _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
