> -----Original Message----- > From: kvmarm-bounces@xxxxxxxxxxxxxxxxxxxxx [mailto:kvmarm- > bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Marc Zyngier > Sent: Tuesday, June 03, 2014 4:26 PM > To: Mathew Li > Cc: kvmarm@xxxxxxxxxxxxxxxxxxxxx > Subject: Re: Few general questions on kvm-arm > > On Tue, Jun 03 2014 at 6:59:25 am BST, Mathew Li <mathew.li100@xxxxxxxxx> > wrote: > > Hi, > > > > I was just trying to understand the KVM-ARM code and ran into the > > following questions. I'm sorry if my questions are really naive. I > > would highly appreciate if someone could shed some light here: > > > > 1. Looking at arch/arm/kvm/arm.c::kvm_arch_vcpu_ioctl_run() function: > > > > ... > > local_irq_disable(); <=== Disable interrupts here. > > > > ... > > > > /************************************************************** > > * Enter the guest > > */ > > trace_kvm_entry(*vcpu_pc(vcpu)); > > kvm_guest_enter(); > > vcpu->mode = IN_GUEST_MODE; > > > > ret = kvm_call_hyp(__kvm_vcpu_run, vcpu); > > > > vcpu->mode = OUTSIDE_GUEST_MODE; > > vcpu->arch.last_pcpu = smp_processor_id(); > > kvm_guest_exit(); > > trace_kvm_exit(*vcpu_pc(vcpu)); > > /* > > * We may have taken a host interrupt in HYP mode (ie > > * while executing the guest). This interrupt is still > > * pending, as we haven't serviced it yet! > > * > > * We're now back in SVC mode, with interrupts > > * disabled. Enabling the interrupts now will have > > * the effect of taking the interrupt again, in SVC > > * mode this time. > > */ > > local_irq_enable(); <=== Enable interrupts here. > > > > /* > > * Back from guest > > > > *************************************************************/ > > > > So in the code above, we disable the interrupts and then run the guest > > code, meaning guest is running while interrupts are disabled if that > > is the case then as per the comment above how can "We may have taken a > > host interrupt in HYP mode", I mean interrupts were not even enabled > > so how can the pcpu running the guest be interrupted? > > Here, we've disabled interrupts at EL1. We then jump to EL2 using HVC, > interrupts are disabled by virtue of interrupts being turned off on exception > entry. > > When we configure the system to enter the guest, we sety the HCR to handle > physical interrupt at EL2. We then ERET into the guest. At that point physical > interrupts will be taken directly into EL2, exiting the guest. > > > 2. Looking at the code in virt/kvm/arm/vgic.c, it looks like we use > > maintenance interrupt to update our in-memory data structures when > > guest EOIs the interrupt. That would mean, we would exit the VM every > > time guest does an EOI. Is that correct? > > Only when we use level interrupts. Do you mean that it exit on EOI for level interrupt and not for edge/msi interrupts? Can you please explain how vgic send next available interrupt of lower or same priority if not exit on EOI for msi/edge interrupt? Thanks -Bharat > > > 3. What is vmid? Why is it needed? Sorry to ask if it is obvious but I > > cannot seem to get my head around that? > > I think you need to read a bit of the ARM ARM. Basically, they serve the same > purpose as ASIDs, at the VM level. > > > 4. While injecting an interrupt into the guest, we update our in > > memory data structures and then call vgic_kick_vcpus(). If the vcpu is > > already running then this function sends an IPI to the the pcpu > > running the vcpu which basically forces vcpu to exit and on the way > > back to continuing the guest we update the guest's interrupts' view > > leading to raising a virtual interrupt to the guest. Is my > > understanding correct here? > > Yes. > > M. > -- > Jazz is not dead. It just smells funny. > _______________________________________________ > kvmarm mailing list > kvmarm@xxxxxxxxxxxxxxxxxxxxx > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
