Thanks for all the answers Marc. I had one more question: Theoretically, can a pcpu running in kernel mode (i.e. non-HYP mode) write to the list register in vcpu control interface of another pcpu (i.e. different from the writing pcpu)? On Tue, Jun 3, 2014 at 6:31 AM, Marc Zyngier <marc.zyngier@xxxxxxx> wrote: > On Tue, Jun 03 2014 at 2:25:10 pm BST, "Bharat.Bhushan@xxxxxxxxxxxxx" <Bharat.Bhushan@xxxxxxxxxxxxx> wrote: >>> -----Original Message----- >>> From: Marc Zyngier [mailto:marc.zyngier@xxxxxxx] >>> Sent: Tuesday, June 03, 2014 5:40 PM >>> To: Bhushan Bharat-R65777 >>> Cc: Mathew Li; kvmarm@xxxxxxxxxxxxxxxxxxxxx >>> Subject: Re: Few general questions on kvm-arm >>> >>> On Tue, Jun 03 2014 at 12:10:28 pm BST, "Bharat.Bhushan@xxxxxxxxxxxxx" >>> <Bharat.Bhushan@xxxxxxxxxxxxx> wrote: >>> >> > 2. Looking at the code in virt/kvm/arm/vgic.c, it looks like we use >>> >> > maintenance interrupt to update our in-memory data structures when >>> >> > guest EOIs the interrupt. That would mean, we would exit the VM >>> >> > every time guest does an EOI. Is that correct? >>> >> >>> >> Only when we use level interrupts. >>> > >>> > Do you mean that it exit on EOI for level interrupt and not for >>> > edge/msi interrupts? >>> >>> Exactly. >>> >>> > Can you please explain how vgic send next available interrupt of lower >>> > or same priority if not exit on EOI for msi/edge interrupt? >>> >>> Look at point 4 of Mathew's description. When injecting the >>> interrupt, you kick >>> the vcpu to force it to reload its state. >>> >>> Additionally, if you have more pending interrupts than your list >>> registers can contain, you set the underflow trigger for the >>> maintainance interrupt, >> >> Let us take an example; Say There are 2 interrupts which needed to be >> injected to guest. >> - kick vcpu >> - reload state of vcpu and now guest can see 2 interrupts. >> - Guest might disable the interrupt while handling above mentioned interrupt >> - 3rd interrupt requires to be injected to guest. >> - host does kick vcpu >> - Will the 3rd interrupt will be seen to guest now? Or is this the >> point where we set a underflow trigger? > > If there is space left in the list registers and the the interrupt is > not disabled (I cannot really tell from your description above), then it > will be visible by the guest. > >> - Now when guest re-enable interrupt then it will exit to kvm and kvm >> will reload new state? > > Assuming your talking about enabling/disabling specific interrupts, then > yes. We always trap on GICD access. > >>> resulting >>> in an exit when you can reload new pending interrupts. >> >> What do we mean by "exit when you can reload new pending interrupts", >> I mean how we know that now we should reload new state ? > > Because that's what the vgic code does: its very job is to track > interrupts and inject what needs to be injected. > > At that stage, I suggest you take a look at the code and become familiar > with how it works. > > Thanks, > > M. > -- > Jazz is not dead. It just smells funny. _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
