On 04/06/14 13:58, Christoffer Dall wrote: > On Tue, Jun 03, 2014 at 05:39:16PM +0100, Marc Zyngier wrote: >> On Tue, Jun 03 2014 at 5:24:01 pm BST, Mathew Li <mathew.li100@xxxxxxxxx> wrote: >>> Thanks for all the answers Marc. I had one more question: >>> >>> Theoretically, can a pcpu running in kernel mode (i.e. non-HYP mode) >>> write to the list register in vcpu control interface of another pcpu >>> (i.e. different from the writing pcpu)? >> >> There are two things here: >> - Not sure if you could write to the GICH range from EL1. I don't see >> anything in the spec that forbids it, but that clearly contrary to the >> spirit of the architecture. > > FWIW, this actually works just fine on a TC2. Yeah, I don't think the source EL is being carried out on the bus, only the S/NS bit. But that's not very nice, and definitely impossible with GICv3 and system registers. M. -- Jazz is not dead. It just smells funny... _______________________________________________ kvmarm mailing list kvmarm@xxxxxxxxxxxxxxxxxxxxx https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
