On 29/06/17 15:23, Toebs Douglass wrote: > On 29/06/17 16:18, Andrew Haley wrote: >> Well, yeah. We can only really blame ARM for this: they provided a >> double-word CAS but no way to define a double-word atomic load which >> does not also store. I hesitate to place blame on the ARM architects, >> a splendid and diligent bunch, but there it is. I have no idea why >> LDXP doesn't work as an atomic load, but it does not. > > Actually, I have a bone to pick with them - the instruction to find out > the ERG size is privileged. As such, unless you know better, you have > to assume the worst case of 2048 bytes. This makes lock-free data > structure state and element structs huge. What for? Just assume that it's a cache line, and if that just happens to run slowly, so what? The user has bought the wrong hardware. And people who make hardware like that should be punished in the profit margin... > It would be enough of a pain to have to make alignment run-time, but you > could do it if you could get ERG size - *but you can't even get ERG size*. > > Ahhh, face palm, etc. I think you can blame that one on kernel architects: it should be possible for them to read the information and tell you. Do they not? -- Andrew Haley Java Platform Lead Engineer Red Hat UK Ltd. <https://www.redhat.com> EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671
