Re: Where does 1586 and i686 break?

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Jean Francois Martinez wrote:

On Sun, 2003-06-08 at 06:28, William Hooper wrote:


Audioslave - 7M3 - Live said:

William Hooper wrote:

Don't forget the Pentium Pro is actually the start of the i686 chain.


The version of the 2.5.70 kernel with MMX seemed to be sort of sluggish. The 686 compiled Red Hat versions seem to work alright. My processor information is below. Which is part of my confusion.

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 5
model name      : Pentium II (Deschutes)
stepping        : 0
cpu MHz         : 233.293
cache size      : 512 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca
cmov pat pse36 mmx fxsr
bogomips        : 465.30

The family being 6 and the model being 5 add even more to my confusion.
I'll have to check out what a pentium pro actually is.

If it makes any difference to you: [whooper@xxxxxxxx whooper]$ cat /proc/cpuinfo processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 1 model name : Pentium Pro stepping : 9 cpu MHz : 199.435 cache size : 256 KB fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 2 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov bogomips : 398.13


There is no such thing as a PII without MMX.  The only i686 processor
without MMX is the P-Pro.


Thanks for the P-Pro as the starting point for the split to the i686. My coppermine works great with that archetecture. The Deschutes confused me the most with the Celeron also being a PII.

I'll try to compile my next kernel as an i686, then another as an i586,
to see which is the best for this slow machine.

thanks,

Jim

A number of people have stated that code optimized for the i586 runs slower on an i686 than either i386 or i686 code. IIRC it has to do with how the i686 does branch prediction... or maybe it has to do with the code cache, I don't remember. I probably could look it up in my "The Intel Microprocessors" book[1], but I don't recall if it covers the i686.

[1] Interesting trivia since I recognize you from the COLUG group, the
author of this text book, Barry B. Brey, taught at DeVry on Alum Creek Dr.
It was interesting having a class where the professor could quote page
numbers from memory because he wrote the text book.  I don't know if he is
still there or not (his home page is a little out of date).



Your assertions are true but another reason is the
relative speeds of  instructions.

Let's imagine that there are two ways to do a thing:
-One with two instructions we will call A and B
-One with a single instruction we will call C

Now assume that on the 386 and the P6 family all three instructions have the same speed while in the i586
C is three times slower than A and B.
That means that code optimized for I586 will use the
A+B combo and thus will be slower on a P6 than code
optimized for the 386 who will use the C instruction


Copying blocks of memory is an example of a task who
will be faster on a P6 if it is done  the 386 way
than if it is done the Pentium way.

JFM





I guess that optimization for instructions, that have the same purpose, would be a real headache. The comparison above was easy to understand. About the proffresor at Devry in southern Columbus, I guess if he wrote the instructions, it would be pretty much a recital for him. Not to mention repetative teaching on the subject.

Thanks,

Jim




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