On Sat, 7 Apr 2012, Jonas Gorski wrote: > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > > index bda8eb2..a08e75d 100644 > > --- a/arch/mips/mm/c-r4k.c > > +++ b/arch/mips/mm/c-r4k.c > > @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) > > c->icache.linesz = 2 << lsize; > > else > > c->icache.linesz = lsize; > > - c->icache.sets = 64 << ((config1 >> 22) & 7); > > + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); > > Why this change? According to the 1074K datasheet it is still 64 * > 2^S, so to me it looks like the previous version was correct. Also > adding first and then masking looks really wrong, and will produce > wrong results for 0x7. FWIW the change looks correct to me. The 3-bit field means 32 for 7, 64 for 0, 128 for 1, etc., up to 4096 for 6. It used to be reserved for 7 in older versions of the architecture spec (rev. 3.05 referred here). Likewise the data cache. Of course it should be sent as a separate change too, even if the 1074K relies on it (which I suppose is why it's been included here). Maciej
