Hi, On 6 April 2012 19:57, Steven J. Hill <sjhill@xxxxxxxx> wrote: > From: "Steven J. Hill" <sjhill@xxxxxxxx> > > This patch adds support for detecting and using 1074K cores. > Signed-off-by: Steven J. Hill <sjhill@xxxxxxxx> > > (snip) > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index bda8eb2..a08e75d 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) > c->icache.linesz = 2 << lsize; > else > c->icache.linesz = lsize; > - c->icache.sets = 64 << ((config1 >> 22) & 7); > + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); Why this change? According to the 1074K datasheet it is still 64 * 2^S, so to me it looks like the previous version was correct. Also adding first and then masking looks really wrong, and will produce wrong results for 0x7. > c->icache.ways = 1 + ((config1 >> 16) & 7); > > icache_size = c->icache.sets * > @@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) > c->dcache.linesz = 2 << lsize; > else > c->dcache.linesz= lsize; > - c->dcache.sets = 64 << ((config1 >> 13) & 7); > + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); See above. > c->dcache.ways = 1 + ((config1 >> 7) & 7); > > dcache_size = c->dcache.sets * > (snip) Jonas
