Hi Bob,
Since txstate will use dma mode1 at default to load fifo, for blackfin
we should set TXCOUNT register[1] before starting dma mode1, please
test the patch below.
BTW, the patch adjust the register write sequence according to [1], in fact
we should write TXCSR first, then start DMA.
[1], 'Peripheral Mode, Bulk IN, Transfer Size Known' section of
'USB OTG CONTROLLER' chapter.
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 9cfd18b..fe5281d 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -317,10 +317,6 @@ static void txstate(struct musb *musb, struct
musb_request *req)
else
musb_ep->dma->desired_mode = 1;
- use_dma = use_dma && c->channel_program(
- musb_ep->dma, musb_ep->packet_sz,
- musb_ep->dma->desired_mode,
- request->dma + request->actual, request_size);
if (use_dma) {
if (musb_ep->dma->desired_mode == 0) {
/*
@@ -347,6 +343,14 @@ static void txstate(struct musb *musb, struct
musb_request *req)
csr &= ~MUSB_TXCSR_P_UNDERRUN;
musb_writew(epio, MUSB_TXCSR, csr);
+
+#ifdef CONFIG_BLACKFIN
+ musb_writew(epio, MUSB_TXCOUNT, request_size);
+#endif
+ use_dma = c->channel_program(
+ musb_ep->dma, musb_ep->packet_sz,
+ musb_ep->dma->desired_mode,
+ request->dma + request->actual, request_size);
}
}
thanks,
--
Lei Ming
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