On 9.12.2020 20.54, Ross Zwisler wrote: > On Wed, Dec 09, 2020 at 03:11:14PM +0200, Mathias Nyman wrote: > <> >> I was testing with Andrzej's script against a g_zero gadget. >> I could trigger many similar issues as those he reported, but not this >> dequeue issue you see. >> >> The rewrite resolved all issues I saw. Script was running without issues >> over night. (tested against both USB2 and USB3). >> >> I haven't tried with two devices simultaneously, I could try that. >> >> Could you share more details about the system you have, what xhci >> controller do you have? > > Sure. I'm running with the following CPU: > > Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz I was able to reproduce the issue with two USB devices on a different system. I saw that the new incorrect dequeue pointer sometimes had the higher 32 bits incorrect while the lower bits were correct. So this looks like a memory access order issue. The command TRB is 16 bytes. The xhci driver writes it in four 4 byte chunks. Even if the driver writes the chunk that sets the cycle bit last, handing the TRB over to the controller, it appears that the actual write order can be different. The controller ends up reading a command TRB with updated cycle bit but old bogus values in the "new dequeue pointer" field. Adding a write memory barrier before writing the cycle bit solved the issue in my case. Whole patch series is updated, added write memory barrier, and rebased on 5.10. It can be found force-updated in the same rewrite_halt_stop_handling branch: git://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git rewrite_halt_stop_handling https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=rewrite_halt_stop_handling Does this work for you? -Mathias
