On Mon, Feb 22, 2016 at 12:42:59PM +0100, Oleksij Rempel wrote: > Am 22.02.2016 um 12:09 schrieb Mark Brown: > > Oh, so this isn't SPI_READY? > Not 100%. > According to TI documentation, transfer initiated by master looks like: > 1. Master: SPIx_CS (on) > 2. Slave: SPIx_READY (on) > 3. Master: Date transfer > 4. Slave: SPIx_READY (off) > 5. Master: SPIx_CS (off) > Bosch version of 5-wire transfer initiated by master: > 1. Master: SPIx_CS (on) > 2. Slave: SPIx_REQUEST (on) > 3. Master: Date transfer > 4. Master: SPIx_CS (off) <----- different order. > 5. Slave: SPIx_REQUEST (on) <----- I can't tell the difference between these two cases. In the first case the device gets busy after the data is transferred, in the second case it never changes the request line but really there's no meaningful difference I can see.
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