Am 22.02.2016 um 12:09 schrieb Mark Brown: > On Sat, Feb 20, 2016 at 10:40:52PM +0100, Oleksij Rempel wrote: > >> I would need some naming suggestions (we call our protokol SSI). It >> looks like the protocol used by us has some differences with Davinci. >> The Dav. using SPI_READY line only >> to allow or pause transmission (fix me if i'm wrong) >> We call it Request line and use it to: Ready to Receive; Receive >> Finished; and Request data shift by slave. > > Oh, so this isn't SPI_READY? Not 100%. According to TI documentation, transfer initiated by master looks like: 1. Master: SPIx_CS (on) 2. Slave: SPIx_READY (on) 3. Master: Date transfer 4. Slave: SPIx_READY (off) 5. Master: SPIx_CS (off) Bosch version of 5-wire transfer initiated by master: 1. Master: SPIx_CS (on) 2. Slave: SPIx_REQUEST (on) 3. Master: Date transfer 4. Master: SPIx_CS (off) <----- different order. 5. Slave: SPIx_REQUEST (on) <----- > >> In this case probably spi framework need to be extended with kind of >> request call back. If data is currently not transmitted and Req line is >> not used for flow control, then call driver specific function to >> initiate data shift. > > This is sounding awfully like SPI slave support? Not completely. Transfer initiated by Slave has only one difference to Master transfer. Bosch version of 5-wire transfer initiated by slave: 1. Slave: SPIx_REQUEST (on) <----- different order. 2. Master: SPIx_CS (on) <---- 3. Master: Date transfer 4. Master: SPIx_CS (off) 5. Slave: SPIx_REQUEST (off) -- Regards, Oleksij
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