On Tue, Feb 08, 2022 at 02:33:16PM +0000, Charles Keepax wrote: > On Tue, Feb 08, 2022 at 01:56:20PM +0000, Mark Brown wrote: > > My understanding was that they'd mixed interrupt handling in as a > > bitfield in another register. > Eek.. what a courageous choice. I guess that might work as > long as there is only a single IRQ status bit in the register, > if there are multiple bits this really needs more complex > handling, like you basically need the old behaviour for the > IRQ part of the register, and the new behaviour for the not > IRQ part of the register. So perhaps a new mask to denote which > bit of the register is being used for IRQ stuff? Yeah, I think that's what I misread the code as doing.
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