On Tue, Feb 08, 2022 at 01:50:36PM +0000, Charles Keepax wrote: > Apologies for the multiple emails, yeah looking at this I think > need some more information on how the hardware that patch was > addressing works. I don't quite understand what was wrong with > the old code even in the inverted case, the old code wrote a 1 to > every bit except the interrupt being cleared which gets a 0. This > feels like how I would have thought a write 0 to clear IRQ would > work, you don't want to clear any other bits so you write 1 to > them. > The update_bits is really problematic as even in the write 0 to > clear case, if a new interrupt asserts between the regmap_read > and regmap_write that make up the update_bits, you will clear that > new interrupt without ever noticing it. My understanding was that they'd mixed interrupt handling in as a bitfield in another register.
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