On Tue, Feb 08, 2022 at 01:39:57PM +0000, Charles Keepax wrote:
> On Tue, Feb 08, 2022 at 01:29:55PM +0100, Marek Szyprowski wrote:
> > Hi Prasad,
> >
> > On 19.01.2022 15:29, Prasad Kumpatla wrote:
> > > With the existing logic by using regmap_write() all the bits in
> > > the register are being updated which is not expected. To update only the
> > > interrupt raised bit and not tocuhing other bits, replace regmap_write()
> > > with regmap_irq_update_bits().
> > >
> > > This patch is to fix the issue observed in MBHC button press/release events.
> > >
> > > Fixes: 3a6f0fb7b8eb ("regmap: irq: Add support to clear ack registers")
> > > Signed-off-by: Prasad Kumpatla <quic_pkumpatl@xxxxxxxxxxx>
> >
> > There is something wrong with this patch. Since it landed in linux-next
> > (20220204) I get an interrupt storm on two of my test devices:
> >
> > 1. ARM 32bit Exynos4412-based Trats2 ("wm8994-codec wm8994-codec: FIFO
> > error" message)
> >
> > 2. ARM 64bit Exynos5433-based TM2e ("arizona spi1.0: Mixer dropped
> > sample" message)
> >
> > Definitely the interrupts are not acknowledged properly. Once I find
> > some spare time, I will check it further which regmap configuration
> > triggers the issue, but it is definitely related to this patch.
> > Reverting it on top of current linux-next fixes the issue.
> >
>
> Yeah I was just looking at this patch it looks a bit weird. Like
> most IRQ acks are write 1 to clear, so doing an update_bits seems
> unlikely to work, as it will ack every pending interrupt. As the
> whole idea of doing a regmap_write was to only write 1 to the bits
> that need ACKed.
>
> I suspect what is needed here is the inverted case wants an
> update bits but the normal case needs to stay as a regmap_write.
>
Apologies for the multiple emails, yeah looking at this I think
need some more information on how the hardware that patch was
addressing works. I don't quite understand what was wrong with
the old code even in the inverted case, the old code wrote a 1 to
every bit except the interrupt being cleared which gets a 0. This
feels like how I would have thought a write 0 to clear IRQ would
work, you don't want to clear any other bits so you write 1 to
them.
The update_bits is really problematic as even in the write 0 to
clear case, if a new interrupt asserts between the regmap_read
and regmap_write that make up the update_bits, you will clear that
new interrupt without ever noticing it.
Thanks,
Charles
