Hi Stephen, > -----Original Message----- > From: Biju Das > Sent: 07 March 2025 07:02 > Subject: RE: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock > > Hi Stephen, > > > -----Original Message----- > > From: Stephen Boyd <sboyd@xxxxxxxxxx> > > Sent: 06 March 2025 22:37 > > Subject: RE: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for > > coupled clock > > > > Quoting Biju Das (2025-03-06 02:10:50) > > > > From: Stephen Boyd <sboyd@xxxxxxxxxx> Quoting Biju Das (2025-03-03 > > > > 03:04:19) > > > > > The spi and spix2 clk share same bit for clock gating. Add > > > > > support for coupled clock with checking the monitor bit for both the clocks. > > > > > > > > Could you add an intermediate parent clk of both spi and spix2 > > > > that only handles the enable bit for clock gating? Then the enable > > > > count handling would be in the core > > clk code. > > > > > > The parent clock rate of spi and spix2 are different. If we use an > > > intermediate parent clk, What clk rate the parent will use?? > > > > Alright, got it. Does the consumer care about the difference between the two clks for the gating > part? > > Although gating bit is same, for some reason their monitor bit is different. So, to confirm clk on > status we need to check respective monitor bits. Parallelly, I will check with hardware team, does it > need to monitor both these bits?? According to hardware team, the spix2 clock is twice the frequency of the spi clock, and the clock ON/OFF period displayed for each bit in the monitor register varies slightly due to the difference in frequency. So to check the status after changing the clock ON/OFF register setting, please check the two monitor register bits together Cheers, Biju
