Hi Stephen, Thanks for the feedback. > -----Original Message----- > From: Stephen Boyd <sboyd@xxxxxxxxxx> > Sent: 05 March 2025 23:17 > Subject: Re: [PATCH 1/4] clk: renesas: rzv2h-cpg: Add support for coupled clock > > Quoting Biju Das (2025-03-03 03:04:19) > > The spi and spix2 clk share same bit for clock gating. Add support for > > coupled clock with checking the monitor bit for both the clocks. > > Could you add an intermediate parent clk of both spi and spix2 that only handles the enable bit for > clock gating? Then the enable count handling would be in the core clk code. The parent clock rate of spi and spix2 are different. If we use an intermediate parent clk, What clk rate the parent will use?? The parent of spix2 and grand parent of spi are same. It is a mux. Mux->spix2->clk gating Mux->divider->spi->clk gating Cheers, Biju
