Quoting Biju Das (2025-03-06 02:10:50) > > From: Stephen Boyd <sboyd@xxxxxxxxxx> > > Quoting Biju Das (2025-03-03 03:04:19) > > > The spi and spix2 clk share same bit for clock gating. Add support for > > > coupled clock with checking the monitor bit for both the clocks. > > > > Could you add an intermediate parent clk of both spi and spix2 that only handles the enable bit for > > clock gating? Then the enable count handling would be in the core clk code. > > The parent clock rate of spi and spix2 are different. If we use an intermediate parent clk, > What clk rate the parent will use?? Alright, got it. Does the consumer care about the difference between the two clks for the gating part? Presumably it's all the same SPI driver here, so could it ignore the second clk and do something like clk_bulk_enable()? Put another way, why does the consumer care that there are two clks? The hardware seems to want them to be the same thing for gating. > > The parent of spix2 and grand parent of spi are same. It is a mux. > > Mux->spix2->clk gating > Mux->divider->spi->clk gating Is the divider fixed div-2? Are they supposed to be at some ratio with respect to each other?
