RZ/G3E XSPI has 4 clocks{ahb, axi, spi, spix2). spi and xpix share the
same CPG_ON bit, but they have different monitor bit. Added coupled clk to
handle this. The mux smux2_xspi_clk{0,1} used for selecting spi and spix2
clocks and pllcm33_xspi divider to select different clock rates.
Note:
This patch series depend upon[1]
[1] https://lore.kernel.org/all/20250228202655.491035-1-prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx/
Biju Das (4):
clk: renesas: rzv2h-cpg: Add support for coupled clock
clk: renesas: rzv2h-cpg: Add support for static dividers
clk: renesas: r9a09g047: Add support for xspi mux and divider
clk: renesas: r9a09g047: Add XSPI clock/reset
drivers/clk/renesas/r9a09g047-cpg.c | 40 ++++++++++
drivers/clk/renesas/rzv2h-cpg.c | 112 +++++++++++++++++++++++++++-
drivers/clk/renesas/rzv2h-cpg.h | 34 ++++++++-
3 files changed, 181 insertions(+), 5 deletions(-)
--
2.43.0
