[PATCH 2/4] clk: renesas: rzv2h-cpg: Add support for static dividers

[Biju Das <biju.das.jz@xxxxxxxxxxxxxx>]

Add support for static dividers that does not need rmw operation.
This will avoid unnecessary memory allocation and using associated
legacy APIs.

Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
 drivers/clk/renesas/rzv2h-cpg.c | 29 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h |  7 +++++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 19fe225d48ed..42a517e11d42 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -349,6 +349,32 @@ rzv2h_cpg_ddiv_clk_register(const struct cpg_core_clk *core,
 	return div->hw.clk;
 }
 
+static struct clk * __init
+rzv2h_cpg_sdiv_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv)
+{
+	struct ddiv cfg_ddiv = core->cfg.ddiv;
+	const struct clk *parent;
+	const char *parent_name;
+	struct clk_hw *clk_hw;
+
+	parent = priv->clks[core->parent];
+	if (IS_ERR(parent))
+		return ERR_CAST(parent);
+
+	parent_name = __clk_get_name(parent);
+	clk_hw = clk_hw_register_divider_table(priv->dev, core->name,
+					       parent_name, 0,
+					       priv->base + cfg_ddiv.offset,
+					       cfg_ddiv.shift, cfg_ddiv.width,
+					       core->flag, core->dtable,
+					       &priv->rmw_lock);
+
+	if (IS_ERR(clk_hw))
+		return ERR_CAST(clk_hw);
+
+	return clk_hw->clk;
+}
+
 static struct clk * __init
 rzv2h_cpg_mux_clk_register(const struct cpg_core_clk *core,
 			   struct rzv2h_cpg_priv *priv)
@@ -451,6 +477,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
 	case CLK_TYPE_DDIV:
 		clk = rzv2h_cpg_ddiv_clk_register(core, priv);
 		break;
+	case CLK_TYPE_SDIV:
+		clk = rzv2h_cpg_sdiv_clk_register(core, priv);
+		break;
 	case CLK_TYPE_SMUX:
 		clk = rzv2h_cpg_mux_clk_register(core, priv);
 		break;
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 4a568fef905d..1905e3a4afad 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -115,6 +115,7 @@ enum clk_types {
 	CLK_TYPE_FF,		/* Fixed Factor Clock */
 	CLK_TYPE_PLL,
 	CLK_TYPE_DDIV,		/* Dynamic Switching Divider */
+	CLK_TYPE_SDIV,		/* Static Switching Divider */
 	CLK_TYPE_SMUX,		/* Static Mux */
 };
 
@@ -142,6 +143,12 @@ enum clk_types {
 		.flag = CLK_DIVIDER_HIWORD_MASK)
 #define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
 	DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable)
+#define DEF_SDIV(_name, _id, _parent, _ddiv_packed, _dtable) \
+	DEF_TYPE(_name, _id, CLK_TYPE_SDIV, \
+		.cfg.ddiv = _ddiv_packed, \
+		.parent = _parent, \
+		.dtable = _dtable, \
+		.flag = CLK_DIVIDER_HIWORD_MASK)
 #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \
 	DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \
 		 .cfg.smux = _smux_packed, \
-- 
2.43.0