That's what I expected too. The issue with the CS being held low so long makes me think there is a little bit more to it. PIO transfers show the same issue with CS so I'm going to try to fix that before looking at DMA again. On 6 August 2016 at 00:19, Chris Brandt <Chris.Brandt@xxxxxxxxxxx> wrote: >> Not a massive difference but at 10MHz (in reality >> ~8.6MHz) the delay between bytes goes from 1.36us down to 1.24us. > > Really??? > > You're experiment was to load up the FIFO (8 bytes) using the DMA which would make me think that you would see bursts of fast data. > > --[][][][][][][][]---delay---[][][][][][][][]---delay---[][]etc... > > But, it sounds like there is still a delay between bytes > > --[]--[]--[]--[]--etc... > > That surprises me. > > > -Chris
