RE: spi-rspi mixes DMA and PIO transfers causing PIO transfer to fail.

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> Not a massive difference but at 10MHz (in reality
> ~8.6MHz) the delay between bytes goes from 1.36us down to 1.24us.

Really???

You're experiment was to load up the FIFO (8 bytes) using the DMA which would make me think that you would see bursts of fast data.

--[][][][][][][][]---delay---[][][][][][][][]---delay---[][]etc...

But, it sounds like there is still a delay between bytes

--[]--[]--[]--[]--etc...

That surprises me.


-Chris




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