Well, it's a 16 byte FIFO, so if you can just fill it up and leave that's the easiest from a SW/HW standpoint. However, if you just used DMA every time, it would still finish just as fast without any CPU involvement so that's the same. So, maybe using the FIFO instead of DMA was a fun idea, but I don't see the technical advantage, so maybe make __rspi_can_dma always return true is fine (unless someone can think of an idea why it's better to use the FIFO instead of DMA for transfers under 16 bytes) The only other thing to do would be to add an extra flag (in struct rspi_data ) that keeps track if the current transfer is PIO or DMA. I've done that before for things like I2C drivers where doing DMA is hard for small packets. But, then you are adding more code and potential new bugs. Chris -----Original Message----- From: linux-renesas-soc-owner@xxxxxxxxxxxxxxx [mailto:linux-renesas-soc-owner@xxxxxxxxxxxxxxx] On Behalf Of Daniel Palmer Sent: Wednesday, August 03, 2016 5:15 PM To: linux-renesas-soc@xxxxxxxxxxxxxxx Subject: spi-rspi mixes DMA and PIO transfers causing PIO transfer to fail. I got DMA working on the RZ/A1H and started to notice this: spi_master spi0: receive timeout What seems to be happening is that there is a DMA transfer for the SPI bus happening so the interrupts are masked. A small transfer that is smaller than the fifo size comes along so __rspi_can_dma returns false and a PIO transfer is started but the interrupt to say it's finished is handled by the DMA controller so the spi driver never sees that it finished. Making __rspi_can_dma always return true makes the problem go away. Does anyone have any suggestions to fix it properly? I'm not on the list so please CC me. Cheers, Daniel
