> The DMA controller in the RZ/A1 can apparently read a long from the source in one > transaction and feed it too the destination as 4 byte writes so I'm thinking maybe > I can setup the DMA controller to read 2 longs and write that as 8 bytes in one go > so that each DMA transaction fills the SPI controller's FIFO. Interesting experiment. If you try it, let me know how it goes. Chris
