On 11/9/2018 4:57 PM, Andrei Danaila wrote:
Unfortunately, I cannot change the IP on the FPGA to add more BARs either, the whole thing is locked down.
Not the best hardware. OK. I am running out of ideas. It doesn't play nice with the driver development model. One idea is to have a parent PCI driver to allocate BAR space and have children platform devices that you create at runtime. You can point to arbitrary address in the system memory map and an IRQ using the platform devices. Though, it might have some alignment requirement in order to be able to make MMU mappings.
