Thanks Sinan, I thought of that as well, unfortunately that it is not possible since the FPGA IP block is proprietary from a 3P vendor and lumps everything under one function with no option of adding additional functions. On Fri, Nov 9, 2018, at 4:32 PM, Sinan Kaya wrote: > On 11/9/2018 4:22 PM, Andrei Danaila wrote: > > A couple of questions: > > > > 1. Is this the correct software flow for managing multiple devices exposed by a PCIe BAR0 address space? > > If not, what is the correct flow? > > If yes, any ideas on what may be going wrong? > > General practice is to create a PCI Physical Function for each sub-functionality > (I2C/UART/DMA etc.) so that individual drivers can claim their own PCI device > and its own BAR space without sharing resources.
